OpenCL software development kit targets FPGA accelerator boards

July 01, 2014 // By Graham Prophet
Altera and its board partners have a combined offering that they claim will accelerate development of high-performance computing, networking and SoC applications; an OpenCL development flow is capable of delivering “prototypes in minutes”.

Altera says it has simplified a programmer's ability to accelerate algorithms in FPGAs, with its SDK for OpenCL version 14.0, that includes a rapid prototyping design flow that enables users to prototype designs in minutes on an FPGA accelerator board. Development of FPGA-based applications is assisted by reference designs, reference platforms and FPGA development boards that are supported by Altera’s OpenCL solution. These reference platforms also streamline the development of custom FPGA accelerators to meet specific application requirements.

Altera offers a publicly available, OpenCL conformant software development kit (SDK) that allows programmers to develop algorithms with the C-based OpenCL language and harness the performance and power efficiencies of FPGAs. A rapid prototyping design flow included in the Altera SDK for OpenCL version 14.0 allows OpenCL kernel code to be emulated, debugged, optimised, profiled and re-compiled to a hardware implementation in minutes. The re-compiled kernels can be tested and run on an FPGA immediately, saving programmers weeks of development time.

Altera and its board partners further simplify the experience of getting applications up and running using FPGA accelerators by offering a broad selection of Altera-developed reference platforms, reference designs and FPGA accelerator boards. Altera provides a variety of design examples that demonstrate how to describe applications in OpenCL, including OPRA FAST Parser for finance applications, JPEG decoder for big data applications and video downscaling for video applications.

Design teams that want to create custom solutions that feature a unique set of peripherals can create their own custom FPGA accelerators and save significant development time by using Altera-developed reference platforms. The reference platforms include an SoC platform for embedded applications, a high-performance computing (HPC) platform and a low-latency network enabled platform which uses IO Channels.

Additional enhancements made to the Altera SDK for OpenCL version 14.0 include:

• Production support for IO Channels that allow streaming data into and out of the FPGA as well as kernel channels allowing the result reuse