Altera's Interlaken Look-Aside intellectual property (IP) core has been tested and is compatible with Cavium's NEURON Search Processor. This deployment-ready, pre-verified solution provides networking OEMs a low-latency, high-performance packet interface for use in networking appliances, including routers, switches, firewalls, and security storage. The Interlaken Look-Aside IP core is part of Altera's IP cores which deliver performance, latency and area utilisation when integrated within Arria 10 and Stratix V FPGAs.
Altera's FPGA-based Interlaken Look-Aside solution enables interoperability between a datapath device and a look-aside coprocessor with transfer rates up to 300 Gbps and delivers more than 500 million packets per second performance. The Interlaken Look-Aside IP is comprised of soft and hardened logic blocks that offer a high degree of user interface, lane and data rate configuration flexibility for optimal integration.
Altera and Cavium tested and verified the Interlaken Look-Aside solution using a Stratix V FPGA and a NEURON Search Processor. The low-latency packet interface and scalable storage space provides high performance and high capacity for Access Control List (ACL) and packet classification applications. An interoperability report is available from Altera that describes the testing methods and performance metrics.
Cavium's NEURON Search Processor family targets high-performance, L2-L4 Network Search applications. The search processor family supports up to 1 million IPv4 and IPv6 rules, delivers hundreds of millions of searches per second and consumes less than 20W max power. The NEURON Search Processor provides flexibility in storing rules and specifying rule table formats.
?Altera and Cavium?s packet classification is a low-risk, high-performance coprocessing solution that our customers require and appreciate,? said Weishan Sun, director of product marketing for Cavium?s NEURON Search Processor Product Line. ?Altera?s Interlaken Look-Aside IP with Cavium?s NEURON Search Processor is an easy to integrate solution that allows our customers to rapidly bring-up their boards, saving on costly engineering hours and materials compared to hardware solutions that are not pre-verified.?