Packet header search function in DRAM and FPGA

July 04, 2016 // By Graham Prophet
Renesas Electronics says it can streamline memory component count in a key aspect of data centre processing, reducing numbers of memory devices to 1/15th with 60% reduction in memory power consumption. The company has implemented a reference design using its LLDRAM-III and FPGA technology, supporting traffic in the 100-Gigabit/sec region

Renesas’ announcement is of a packet header search reference design for 100 Gigabit (Gb) communications devices such as routers, switches, and servers. The design comprises LLDRAM-III (RMHE41A364AGBG) power-efficient, low-latency memory (LLDRAM), proprietary exact-match search IP, and LLDRAM-III controller IP on an FPGA device, and development support tools. FPGAs used have been Xilinx UltraScale Veritex and Kintex devices. It enables 100 Gb traffic packet header search functionality using 1/15th the number of memory devices that would be required in a configuration employing standard DRAM memory and reduces memory power consumption by 60%.


Data centres, Renesas notes, are switching their traffic speeds from 40 Gb to 100 Gb to support the increasing volume of data, and the increasing number of search entries. However, boosting the speed of network equipment typically brings an increase in power consumption, and this raises issues such as device package temperature and power costs. Also, widespread adoption of SDN and NFV brings the need for frequent modification of the network configuration by software and creates demand for network equipment supporting flexible reconfiguration. Against this background, Renesas has developed a power-efficient packet header search reference design able to process high-speed traffic. It incorporates an FPGA, allowing flexible network configuration and LLDRAM-III memory capable of storing one million or more search entries. Features of the design include;

- Packet header search of one million entries (an entry is a search key and a destination for packet forwarding) or more in 100Gb traffic using only 2W. LLDRAM-III is a power-efficient type of low-latency memory from Renesas that supports 400 mega accesses (read or write operations) per second and consumes 2W or less to transfer 57.6 Gb of data. By combining this memory with the newly-developed search algorithm from Renesas, it is possible to process 150 million packet header searches per second, as required for 100 Gb Ethernet, using a single LLDRAM-III device. Performing the same processing with a configuration using