PCB analysis tool checks EMC and signal integrity issues

September 03, 2012 // By Julien Happich
Design engineers dealing with electromagnetic compatibility (EMC) and signal integrity (SI) of PCBs, can now employ CST's Boardcheck tool to get a quick overview of potential problems in their layout.

CST Boardcheck supports a multitude of popular layout formats such as Cadence Allegro, Zuken CR 5000, Mentor Graphics Expedition and ODB++, which are read-in using the CST Studio Suite import filters.

Once imported, the engineer can check nets critical to the design against a number of individually selectable, industrially well established design rules, in order to ensure the EMC and SI of the design. EMC rules include net reference (net crossing split...), wiring, crosstalk (critical net near I/O net…), decoupling (capacitor density…), and placement. SI rules include net integrity (net length,…) and via integrity (unconnected via pads,…). The tool rapidly generates a report listing all violations and enables the user to highlight the corresponding problematic portions of the design.

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