DesignWare IP for PCI Express delivers critical reliability, availability and serviceability (RAS) features to increase data protection, system availability and issue diagnosis for high performance, data intensive cloud applications. Support for the new PCIe 4.0 v0.5 specification gives designers the ability to start incorporating the latest functionality while meeting high performance 16 GT/sec data transfer speeds.
The new RAS features in the DesignWare IP increase system reliability by using parity and error correcting code (ECC) data protection in conjunction with protocol defined mechanisms to detect and correct errors in the datapath and RAMs. Event counters and statistics monitor system availability, while error injection and silicon debug capabilities help diagnose issues and validate system recovery.
Designers of enterprise systems require increasing levels of bandwidth and that is driving designers to adopt the latest versions of the 16 GT/sec PCIe 4.0 specification. While the PCIe 4.0 specification is under development, Synopsys performs extensive interoperability testing with ecosystem partners to help designers reduce design risk for their initial products with PCIe 4.0.
“Teledyne LeCroy works closely with Synopsys to ensure interoperability between our respective market leading solutions and to ensure compliance to the latest PCIe specifications,” said John Wiedemeier, product marketing manager at Teledyne LeCroy. “By starting interoperability testing early in the specification development process and continuing through specification updates, Teledyne LeCroy and Synopsys are giving designers confidence that the IP will work as expected, thereby reducing their design risk.”
The DesignWare Controller IP for PCIe 4.0 supports multiple lanes (x1 to x16) and multiple datapath widths for optimal configurations, as well as Native, ARM AMBA AXI-3? and AMBA AXI-4 interfaces for integration into systems on chips (SoCs). The DesignWare PHY IP for PCIe 4.0 supports full featured bifurcation and aggregation, offering designers the flexibility either to configure the PHY macro into multiple individual links at 2.5, 5, 8 or 16 GT/sec, or to aggregate the PHY macro up to 16 lanes. Synopsys