PLL with VCO synthesiser ranges to 6.8GHz, boosts base station specs

January 26, 2016 // By Graham Prophet
Analog Devices has added a phased-locked loop (PLL) synthesiser with integrated voltage-controlled oscillator (VCO); the ADF4355 PLL with VCO synthesiser operates up to 6.8 GHz, a frequency band that allows significant margin to industry’s current carrier frequencies.

When designed into cellular base stations, the new PLL synthesiser’s higher frequency and lower VCO phase noise enables wireless service providers to increase call throughput and cell phone coverage and service more users per base station at no significant additional cost. The device’s higher frequency band offers similar throughput advances for makers of point-to-point/point-to-multipoint microwave links, satellite/VSAT systems, industrial and test and measurement systems as well as other wireless equipment.


Block diagram

The integrated VCO has an output frequency ranging from 3.4 to 6.8 GHz. The VCO frequency is connected to divide-by-1, -2, -4, -8, -16, -32, or -64 circuits, which allows the designer to generate RF output frequencies as low as 54 MHz, thereby allowing the ADF4355 to cover a continuous range from 54 to 6800 MHz with no gaps. For applications that require noise isolation, the RF output stage features a mute function that is both pin and software controllable. The ADF4355 can operate in either fractional-N or integer-N mode, and with 38-bit modulus resolution offers exact mode frequency operation, independent of reference input frequency.

In frequency generation applications for wireless and industrial applications, where VCO phase-noise performance plays a pivotal role in determining the overall system performance of the RF signal transmission and receive, the choice of PLL synthesiser for the RF local oscillator (LO) is a key system design consideration. This wideband PLLVCO synthesiser, ADI says, meets the exacting VCO phase noise requirements for frequency generation applications while delivering a cost-competitive alternative to other PLL devices in a smallest-in-class 5 × 5 mm LFCSP package. This combination of features allows designers to reduce risk by ensuring the lowest possible phase noise, extending frequency coverage, shrinking footprint and increasing operating range across temperature.


Evaluation board

Control of all on-chip registers is through a 3-wire interface. The ADF4355 operates with analogue and digital power supplies ranging from 3.15 to 3.45V, with charge pump and VCO supplies