Processor IP for safety-critical automotive gains DSP & cache support

May 12, 2016 // By Graham Prophet
Synopsys has added automotive safety support to its DesignWare ARC EM processors, with DSP and cache configurations to enable smart automotive sensors and controllers. The ASIL D Ready certified ARC EM processors with Safety Enhancement Package integrate safety-critical hardware features including error-correcting code, parity support, user-programmable watchdog timer and lockstep interface.

Synopsys has extened its Safety Enhancement Package (SEP) to its DesignWare ARC EM processors that include cache support and DSP acceleration. The ARC EM4, EM6, EM5D and EM7D cores, combined with the ARC SEP option, have been certified ASIL D Ready by SGS-TÜV Saar, a leading independent certification company. The compact cores incorporate critical safety features such as Error-Correcting Code (ECC) and a programmable watchdog timer for detecting system failures. The SEP option adds a lockstep interface and comprehensive safety documentation that facilitate chip- and system-level ISO 26262 ASIL D compliance. In addition, software developers can accelerate the development of ISO 26262-c ompliant code with the ASIL D Ready certified ARC MetaWare Compiler. The ARC EM cores with SEP are designed to meet the small area and rigorous safety requirements of system-on-chips (SoCs) targeting a broad range of automotive applications including sensors, controllers and advanced driver assistance systems (ADAS).

 

All ARC EM processors are configurable and extensible to meet the performance, power and area requirements of each target application. In 2013 Synopsys introduced the Safety Enhancement Package for ARC EM4 cores to help automotive chip designers meet the specific requirements of the ISO 26262 functional safety standard. Now, to address the evolving processing requirements in automotive applications such as motor control and sensor fusion, the SEP option is being extended to EM processors that support DSP functions and incorporate up to 32 kBytes of instruction and data caches. The company adds that the EM cores with the SEP option are the first cores in their class to be certified ASIL D Ready. The combination of the ARC EM cores' integrated hardware safety features, ASIL certification and safety-related collateral such as a Failure Modes, Effects, and Diagnostic Analysis (FMEDA) report saves automotive designers effort in their SoC development and ISO 26262 certification process.

 

The DesignWare ARC MetaWare Development Toolkit for Safety is a complete solution for developing, debugging and