Push the UVM start button then hit the accelerator - part 1

November 08, 2015 // By Doug Amos, FPGA Consultant
So, you’re STILL not using UVM? Maybe you’ve taken a good look and decided that the Universal Verification Methodology for SystemVerilog (UVM) is not for your team. Maybe, you’ve not got round to taking that close look, but you’ve read a lot of these kinds of articles and been scared off by the warnings that UVM is hard to learn. This article won’t help you learn ANY of it, but it will point you to how you might speed up your UVM learning, your UVM adoption and even your UVM execution throughput.

After all, who needs a steep learning curve on top of all that other verification work? Then there is the uncertainty of the potential return on investment in adopting UVM. Will it really find more bugs or verify your design faster?

Make no mistake, becoming proficient with all the features of UVM takes a couple of weeks of formal training, and a while longer to confidently put what you’ve learned into practice. At the Verification Futures Conference in 2012, Janick Bergeron, one of the fathers of constrained random verification methodology, was asked for some advice on how to learn UVM. The answer was “don’t try to learn all of it”.

A boost up the UVM Learning curve

Remember, you are not alone, pioneering a new methodology; many have walked that path before you and some of those offer guidance to those following behind. For example, Doulos, the well-respected training company, has been teaching UVM classes and helping to define the standards since UVM started, and has created something called “Easier UVM” as a way to accelerate adoption and reuse.

Easier UVM was originally created as a way to help non-experts to learn UVM and to accelerate its adoption after the students return to work. Comprising methodology guidelines and a really useful code generation tool, Easier UVM has already been adopted for real-life projects and tape-outs. John Aynsley, CTO of Doulos, says that the three most common ways that users benefit from Easier UVM in their projects are;

1. Use the code generator purely as a learning tool.

2. Use the code generator and templates to create, develop and maintain all the SystemVerilog code to run UVM.

3. Use the code generator just once in order to create the framework, but then proceed fully manually form then on.

None of these approaches is more correct or recommended than the others; it is simply a matter of choice for each team. However, in all cases, the Easier UVM approach ensures the UVM code is written in a consistent style.

Of course, verification teams need to know what they’re doing with UVM, and expertise is eventually required, but if you are the first advocate for UVM within your team, then Easier UVM will help you gain early success in order to promote the wider use of UVM in other projects.

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