Embedded on-chip, the noise monitor IP block avoids the need to use hand-probing techniques, improving the quality of silicon test results and speeding time-to-market, the company claimed.
The Noise Monitor is described as an extremely small IP block but Rambus did not give dimensions in a particular manufacturing process.
It is integrated directly into the complex IC capable of measuring noise at frequencies up to 6GHz, making it suitable for high data rate applications, as well as those that use package-on-package and 2.5/3D packaging.
When coupled with the Rambus LabStation Validation Platform, designers are able to precisely measure multiple aspects of power supply noise.
While Rambus did not indicate that the IP block had been proven in any particular process the company indicated it is suitable for leading-edge mobile and data center SoCs suggesting it is intended for deployment in leading-edge processes.
"As the system requirements for smartphones, tablets and servers continue to drive higher data rates and reduced power, designers are facing increasingly difficult challenges to accurately measure and characterize SoC power supply noise," said Kevin Donnelly, general manager of the memory and interface division at Rambus, in a statement. "The fast and accurate results delivered by the On-chip Noise Monitor provide designers a better understanding of the affects of noise and circuit performance and an increased confidence in the quality of IC design."
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