Real-time compliance analyser for DDR4, DDR3 and DDR3L memory

October 23, 2013 // By Graham Prophet
Tektronix' MCA4000 provides instantaneous visibility into memory interfaces over long analysis runs for deep insight into memory bus activity

This instrumentation introduction provides real-time memory execution validation capabilities for faster protocol, performance and compliance analysis of JEDEC DDR4, DDR3 and DDR3L memory standards. The MCA4000 protocol compliance and bus protocol analyser, developed by Nexus Technology, a Tektronix partner for memory solutions, provides instantaneous observability of memory interfaces over long periods of time, providing deep insight into memory bus activity.

With DDR4 and DDR3L with higher data rates, lower power consumption and greater capacity, designers face new challenges to validate and debug devices with tighter margins, faster edge rates and complex bus protocols. Tektronix has therefore added real-time execution validation capabilities to its memory analysis portfolio .

The MCA4000 has a dual architecture that enables the detection of protocol violations coupled with the ability to acquire and analyse violations and determine bus performance. The MCA4000 has an integrated protocol analyser that monitors a DDR memory bus at-speed, reporting statistical results on events and violations in real-time. It also has an integrated, full function logic analyser with 1G-cycle acquisition depth. The instrument incorporates a fully programmable front-end that provides the ability to generate oscilloscope-like eye diagrams to graphically illustrate DDR PHY settings, bus integrity and required sample points.

Tektronix' family of probes and interposers are shared between Tektronix 7000 series logic analysers and the MCA4000, providing the ability to view high speed timing, state, protocol and real-time analysis data simultaneously with one single load.

Tektronix; www.tek.com/technology/ddr-test/electrical-validation