Reference design for optical Ethernet system management interfaces

August 08, 2014 // By Graham Prophet
A reference design builds a multi-gigabit IEEE 802.3 MDIO interface controller based on small, low power, programmable logic chips from Lattice’s MachXO3 and ECP5 families.

To quickly implement optical Ethernet designs up to 100 Gb/sec, for IEEE 802.3 Management Data Input/Output (MDIO) interface controllers, reference design RD1194 uses the small, low cost per I/O programmable platform, the MachXO3 family, or the new ECP5 family. The ECP5 features the highest functional density with up to 85k LUTs and SERDES in 10 x 10 mm packages. With their small size and low power, MachXO3 and ECP5 devices are appropriate for implementing I/O expansion, bridging or connectivity needed to deliver Multi gigabit Ethernet applications such as CFP2/4 modules.

Designers can use the reference design to implement a simple Wishbone user logic interface that enables the user to access the PHY registers. It supports MDIO IEEE 802.3 Clause 45/22 master/slave controllers and features pre-amble pattern selection through the input port.

Lattice Semiconductor;