Design Compiler Graphical provides IC designers with visualisation of congested circuit regions and performs automated synthesis optimisations to minimise congestion in these areas. The optimisation technologies it embodies monotonically reduce design area and leakage power by an average of 20% while maintaining timing QoR (quality of results). Design Compiler Graphical shares physical technologies with IC Compiler and IC Compiler II place and route solutions to deliver highly correlated results for timing, area, power and routability, reducing design iterations and trimming critical schedule time.
Tatsuji Kagatani, manager of Design Automation Department at Renesas System Design observes, “Design Compiler Graphical’s significant area and routing congestion reduction, combined with IC Compiler for place and route, enable our design teams to achieve faster timing and smaller area. We have widely deployed Design Compiler Graphical for our products currently using our 40 nanometer process.”