Various data path systems are designed to synchronize with inputs, process them, and provide output. For such designs, if all the unused states are waiting for acquiring the sync state, then the design can do without ever being reset. For designs where the state machine logic has been optimized during synthesis by avoiding logic reduction, resets are essential to prevent the design from starting in a random state.
There are various scenarios apart from the device reboot where the resets are required in real-world designs. Some likely scenarios include:
- If a clock source drops out, then the design should enter the reset until PLL lock is acquired.
- Communication channel must be reset, when the link partner loses sync.
- A user-accessible push button reset.
- Reset from microprocessor after some event, example after expiry of a watch dog timer.
- Partial reconfiguration in modern FPGAs where the swapped logic block must be reset - independently of its environment.
- Use of legacy IP from previous ASICs or an IP vendor requiring reset.
- Reset to start clean simulations.
To achieve better performance, designs nowadays have their data pipelined through chains of flip-flops. For such designs, the usage of reset can be eliminated in the pipelined flops to achieve better area utilization and performance. Choosing reset usage and its strategies in ASIC/FPGA designs require many design considerations such as whether every flip-flop will require a reset, whether to use a synchronous reset or asynchronous reset, how the reset tree will be structured and buffered, how to verify timing of reset tree, how test scan vectors are applied to check functionality of reset and how reset is handled in multi clock domain designs. In this article, we will see the reset usage in Data and Control path in ASIC and FPGA. We will also see how FPGA components such as shift registers, Block RAM, Distributed RAM, and DSP Slices can be used efficiently with proper use of reset.
Reset usage in Data Path & Control Path in ASIC
A common belief of most designers is that all the flops in the design should have a reset. This is not true for data paths. Flip-flops in control path do need a reset but flip-flops in data path can go without it. All these pipelining flip-flops or delay flip-flops don’t need resets. Moreover shift registers, data bus etc. which depend on some resets, to indicate valid data at any time can do without a reset signals.