“Our collaboration with EnSilica not only represents an excellent opportunity to widen the range of platforms supported by Phoenix-RTOS but, we believe, it also releases the full potential of the eSi-RISC processor family,” said Paweł Pisarczyk, CEO of Polish software house Phoenix Systems. “The combination of Phoenix-RTOS and eSi-RISC will give customers a distinct commercial advantage in the upcoming smart grid market by allowing us to prepare fully integrated embedded smart grid solutions. Soon, Phoenix-RTOS will be integrated into a range of smart meters as well as medical devices such cardio-monitors.”
The collaboration between UK-based EnSilica and Phoenix Systems provides an embedded RTOS capable of fully using eSi-RISC’s hardware MMU with memory protection and security features such as data execution protection. It also paves the way for embedded power line and wireless smart grid solutions with the combination of Phoenix Systems’ proposed smart grid software protocol stacks and eSi-RISC’s support for custom instructions accelerating performance and improving PHY layer implementations.
Phoenix-RTOS is a fully proprietary, real-time operating system designed specifically for both single and multicore embedded applications. Its modularity and portability, coupled with a small footprint, virtual memory support and an advanced architecture that implements the latest operating system mechanisms and programming abstractions, are suited to highly configurable soft processor cores like the eSi-RISC family. The fully re-entrant and pre-emptive kernel supports scheduling strategies that allow for the prioritization of critical task execution. Additional components, such as TCP/IP and USB stacks, common file systems and POSIX interface, further leverage its potential for machine-to-machine communication and smart grid applications.
EnSilica’s eSi-RISC family provides a range of high quality, highly configurable embedded processors that are easy to integrate. The processor subsystem is delivered fully targeted to customers’ ASIC technology, thereby reducing integration effort. eSi-RISC processors provide the flexibility to define a range of hardware functions to optimize the silicon area. On–chip memory requirements are reduced through inter-mixed 16-bit and 32-bit instructions, resulting