Segger’s J-Link supports Silicon Labs’ 8051 devices

November 21, 2014 // By Graham Prophet
Segger has added support for Silicon Labs’ 8051 family of 8-bit MCUs to its J-Link family of debug probes. This includes run control as well as download into RAM and flash of all supported devices

J-Link offers highest debug and download performance into RAM and flash memory on all supported targets, a feature which is retained when debugging 8051 devices.

“We are excited to bring the proven reliability and outstanding performance of the J-Link line of debug probes to the 8051 development community. It shows that Segger can not only support 32-bit architectures like ARM, MIPS and RX cores, but also 8-bit architectures and still deliver the same benefits such as ease of use, high performance and direct download to flash memory,” says Alexander Gruener, Product Manager of the SEGGER J-Link family of debug probes.

J-Link is tool chain independent and works with free GDB-based tool chains such as emIDE and Eclipse, as well as commercial IDEs from: Atmel, Atollic, Coocox, Cosmic, Freescale, IAR, KEIL, Mentor Graphics, Microchip, Python, Rowley, Renesas, Tasking and others. With the J-Link family, investments in the debug probe are preserved when changing compiler or even CPU architecture.

J-Link supports multiple CPU families, such as ARM 7, 9, 11, Cortex-M, Cortex-R, Cortex-A as well as Microchip PIC32, and Renesas RX100, RX200, RX600, and 8051; there is no need to buy a new J-Link or new license when switching to a different yet supported CPU family or tool-chain.

Segger; http://segger.com/jlink-8051.html