Self-refresh DRAM on ‘HyperBus’ interface – the HyperRAM memory

July 06, 2016 // By Graham Prophet
Serving, among other possible uses, as an expanded scratchpad memory for high-performance applications, Cypress Semiconductor is sampling a high-speed, self-refresh Dynamic RAM (DRAM) based on Cypress’s low-pin-count (12-pin) HyperBus interface.

The 64Mb HyperRAM serves as an expanded scratchpad memory for rendering of high-resolution graphics or calculations of data-intensive firmware algorithms in automotive, industrial and consumer applications. The devices operate with a read/write bandwidth of up to 333 MBps and are available in 3V and 1.8V supply voltage ranges.


When paired with a Cypress HyperFlash NOR Flash memory, HyperRAM enables a simple and cost-effective solution for embedded systems where both the flash and RAM reside on the same 12-pin HyperBus. Traditional systems with an SDRAM and Dual-Quad SPI solution require upwards of 41 pins on two buses for data transactions. The HyperRAM and HyperFlash solution reduces pin count by at least 28 pins, decreasing design complexity and lowering PCB cost. HyperRAM is a solution for automotive clusters and infotainment, communication equipment, industrial applications and high-performance consumer products.


To accelerate product design cycles, Cypress offers a HyperBus Master Interface Controller IP Package. This controller IP helps designers add support for HyperBus to their Field-Programmable Gate Array (FPGA), Application-Specific Integrated Circuit (ASIC) or Application-Specific Standard Product (ASSP) host controller platform. The Controller IP supports both HyperRAM, as well as HyperFlash products, and is free of charge and royalty-free.


The Cypress 64Mb HyperRAM is sampling now with production beginning in the third quarter of 2016. The devices will be available in a 24-ball, 6-mm by 8-mm ball grid array (BGA) package.


More information on the 64Mb HyperRAM at