Serial interconnect IP for TSMC 20-nm SoC designs

September 20, 2013 // By Graham Prophet
Synopsys has announced a portfolio of interface IP for TSMC’s 20SoC process, enabling designers to reduce power consumption and increase performance for mobile and multimedia SoC designs

Synopsys’s DesignWare IP portfolio for TSMC’s 20 nanometer (nm) system on chip (SoC) process (TSMC 20SoC) includes USB, DDR, PCI Express, and MIPI PHY IP. The IP portfolio has been designed into multiple customers’ SoCs which are ramping to production now. TSMC’s 20SoC process enables designers to reduce the power consumption by up to 25% or increase performance by 30%. The DesignWare IP portfolio is designed to achieve high yield by meeting the requirements of advanced manufacturing design, such as adhering to double patterning layout rules.


As designs migrate to smaller process nodes, such as 20nm and 16nm FinFET, the technology challenges to extend Moore’s Law become increasingly complex. TSMC has implemented double patterning mask technology on its 20SoC process utilising two photo masks, each with half of a pattern, to enable printing of images below the node’s minimum spacing design rules. Synopsys’ development of DesignWare IP at 20nm focused on minimising yield and manufacturability issues while adhering to the standards’ specifications, as well as TSMC’s advanced layout and design rules for manufacturability with double patterning technology.

According to John Koeter, vice president of marketing for IP and systems at Synopsys. “By offering a broad portfolio of IP for the 20nm process, Synopsys enables designers to more easily meet their goals of creating differentiated products with less risk and faster time to volume production, while also reducing the risks associated with moving to the 16nm FinFET process.”