The potential for a clogged network is coming as little surprise. The IEEE Ethernet Bandwidth Assessment Report of 2012 predicted a 100-fold increase in network traffic by 2020, requiring networks to support up to 10 terabits per second. With this prediction, the network will need 400-gigabit-per-second link speeds as early as 2015.
While networking system memory has traditionally relied on legacy DRAM and SRAM connected to line card processors through parallel interfaces, higher capacity line cards supporting transmission rates of 100 Gbps and beyond will require scalability that a serial interface provides.
Legacy memory not only presents bandwidth and access-rate constraints, but also locks network line cards into inefficient pin count, board space and power requirements that add cumulatively to system costs. To break free of these constraints, network design engineers are now designing better alternatives.
Serialising the memory access on networking line cards is rapidly gaining momentum as one of these alternatives because it reduces all three limitations. Furthermore, this approach avoids the commercial and logistical quagmire of the technical panacea known as “multi-chip modules” (MCMs).
MCMs deliver the performance required by using advanced and sophisticated packaging technologies. Once the interconnect challenges are solved the user is still faced with a daunting cooling requirement created by the thermal density of the package. However, the ultimate reason why MCM adoption is limited is because of supply chain logistics and inventory ownership. These issues are not insurmountable for mobile phones where the power is low, unit costs are in the single digit range, the market is huge and the lifetime expectation is only a few years. The networking infrastructure market is at the opposite end of the spectrum by comparison.
Today, line cards in high-speed networks aggregate to 100Gbps or more. Although deployments of these systems have been generating headlines for several years, they are just now evolving from the early adoption phase, where performance won out over power and space