Setting up designs for synthesis; text book covers how to write timing constraints

May 31, 2013 // By Julien Happich
The book “Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)” is authored by Sridhar Gangadharan, senior product director at Atrenta and Sanjay Churiwala, director at Xilinx.

It features a foreword by Dr. Ajoy Bose, chairman, president and CEO of Atrenta and is published by Springer Science+Business Media.

“Timing has become a critical requirement for the highly complex system on chip designs we see today and effective use of SDC is critical to success,” said Sridhar Gangadharan. “I would like to acknowledge Synopsys for their work to develop the Synopsys Design Constraints (SDC) format and their willingness to make it widely available through their TAP-in program.”

The book targets system on chip designers and provides a complete overview of how to create effective timing constraints using SDC, including detailed syntax and semantics, its impact on timing analysis and synthesis and the interaction of timing constraints with the rest of the design flow.

“Our goal was to develop a practical, hands-on guide to writing and understanding timing constraints for system on chip design,” said Sanjay Churiwala. “While there are texts that treat portions of the problem such as synthesis or static timing analysis, there has not been a single, highly detailed source that treats the entire set of timing constraints challenges specifically relating to SDC.”

The book is available through Springer at