Signal integrity analysis of PCBs for multi-gigabit interfaces

January 21, 2016 // By Graham Prophet
Cadence Design Systems’ Sigrity 2016 technology portfolio can, the company says, improve product creation time with an enhanced PCB design and analysis methodology that is suitable for for multi-gigabit interfaces.

To speed up the qualification of a physical design for the USB Implementers Forum (USB-IF) compliance test, the Cadence Sigrity technology portfolio includes automated support for IBIS-AMI model creation, fast and accurate channel model extraction using multiple field solvers, and an automated power-aware signal integrity analysis report to validate a virtual USB 3.1 channel. These technologies, when used together, can save weeks in a design process.

Previously, IBIS-AMI model creation has been a manual process. The Sigrity 2016 technology portfolio now makes use of validated equalisation algorithms used by the Cadence Design IP SerDes PHY team and provides an automated methodology for combining, paramaterising and compiling the algorithms into an executable model. This can increase the pool of engineers capable of efficiently developing SerDes I/O models.

The new “cut and stitch” technology features the ability to create accurate channel models ten times faster by using a mix of hybrid and 3D full-wave field solvers. With minimal manual intervention, the serial link channel can be divided into sections, solved for and automatically stitched together into a single interconnect model. The rapid model extraction technique enables engineers to trade-off various signal routing and layer transition strategies and still meet demanding time-to-market requirements.

Other capabilities that have been enhanced in the portfolio are:

• New quasi-static 3D field solver integrated with 3D full wave and hybrid solver technology available for both IC package and PCB analysis

• Electrical Performance Assessment integrated directly into the IC Package Designer’s layout environment

• Optimised decoupling capacitor schemes updated to Allegro PCB layout

• Improved Power Integrity analysis methodology for PCB designers

These features, Cadence adds, remove the need to manually write and compile code using a software development environment to create SerDes I/O models and that makes modelling of transceivers and interconnects faster.

Cadence; www.cadence.com/news/sigrity2016