Signal processing VPX module with PCIe interface

February 10, 2015 // By Graham Prophet
This high performance DSP and FPGA board for harsh environments from CommAgility, the VPX-D16A4-PCIE is a rugged card in the compact VITA 65, 3U OpenVPX form factor, with a high speed Gen2 PCI Express (PCIe) interface.

Use it in applications such as electronic warfare (EW), software radio, imaging or radar that require very high signal processing performance in the robust VPX form factor for deployment in harsh environments. It is well suited to implementations where it interfaces with other boards based around Intel processors.

The VPX-D16A4-PCIE complements CommAgility’s existing VPX-D16A4, which provides similar functionality, but is aimed primarily at wireless applications. The main difference between the two modules is that the VPX-D16A4-PCIE includes a 10 Gbaud 2x PCIe interface to the VPX backplane for each of the two on-board Texas Instruments (TI) System-on-Chip (SoC) devices, instead of the VPX-D16A4’s 20Gbaud RapidIO links.

The new board is based around a TI TCI6638K2K KeyStone-based SoC and a TI TMS320C6678 SoC, which between them contain sixteen C66x DSP cores and four ARM Cortex-A15 cores, as well as baseband and networking accelerators. The two SoCs are closely coupled with TI’s HyperLink bus as well as Gigabit Ethernet. Each device has its own large 2 Gbytes DDR3 memory bank.

The VPX-D16A4-PCIE is available as either conduction cooled or air cooled versions. For maximum flexibility in interfacing, it supports PCI, Ethernet, CPRI and Multi-Gigabit Transceiver (MGT) to the backplane plus links to RF or analogue I/O. For additional I/O or co-processing, the main DSP is connected via PCI Express and the AIF2 CPRI interface to a Xilinx Kintex-7 K325T FPGA, which also has Gigabit Ethernet and its own backplane MGT connections. The FPGA has multiple LVDS, GPIO and serial connections to the P2 connector to enable interfacing to an RTM with specialised I/O such as multi-channel RF or high speed ADC/DAC interfaces. It also has a PLL for flexible generation of RF clocks from a standard reference clock input.

The main DSP and FPGA both have a large bank of flash memory for application and data storage, with FLASH upgrades and boot selection managed in conjunction with the Board Management Controller for