Fabless suppliers must strive to reduce power consumption of their SoCs to ensure acceptable battery lifetime for the end-users, the company adds. However, even when the appropriate foundry process and silicon IP have been selected, the overall power consumption of SoCs can still be optimised.
Going beyond providing a set of low-power optimised Silicon IP components for the needs of IoT devices, Dolphin Integration addresses the challenge of assembling and verifying the most efficient power management architectures, delivered with the relevant advanced views to enable consistent verifications at SoC level. A number of activity control units provide detailed and safe management of dual voltage and frequency stepping. The image shows an example of IP solutions for wearable connected devices at 55 nm.
Differentiators of Dolphin Integration's consistent Silicon IP offering include:
- The CLICK concept - Composite Logic Island Construction Kit - to build logic, memory and mixed-signal islands for all operating modes thanks to innovative cells
- Power kit library of regulation components: to build an optimised SoC architecture for the lowest power consumption
- Ultra low-power ADCs: for activity tracking or always-on voice detection
- Microcontroller cores ranging from 8051 to 32-bit: for the best trade-off between power consumption and processing power or silicon area
- uLP: ultra Low Power;
- uLL: ultra Low Leakage;
- HD: High Density;
- DV: Dual Voltage;
- RR: Retention Ready.
Dolphin Integration; www.dolphin-ip.com