Single-chip clock IC for wireless base stations

June 16, 2015 // By Graham Prophet
Silicon Labs’ ultra-low phase noise Si5380 clock IC is intended to cut BOM cost, footprint and power in small cell and macro cell applications.

This timing device for Internet infrastructure is positioned as the most highly integrated clock IC available for wireless infrastructure applications including small cell and macro cell base stations. The Si5380 clock generator replaces a low phase noise integer-N clock, voltage-controlled crystal oscillator (VCXO), discrete loop filters and voltage regulator components with a single-chip device. The Si5380 clock claims comparable phase noise performance to discrete conventional solutions while delivering breakthrough advancements in solution footprint, bill of materials (BOM) cost, power consumption, performance and ease of use.

The Si5380 clock uses Silicon Labs’ fourth-generation DSPLL technology to provide a purpose-built solution optimised for next-generation small cells and macro cell remote radio head (RRH) designs. The DSPLL dual-loop mixed-signal architecture integrates a single 15 GHz analogue voltage-controlled oscillator within a digital phase-locked-loop (PLL) architecture that eliminates the need for discrete loop filters and low-drop-out (LDO) regulators. The resulting clock solution combines ultra-low phase noise clock synthesis with PLL integration.

The Si5380 takes one-third the footprint and has 30% lower power consumption than competing VCXO-based clock IC solutions. Power-efficient timing components are especially important for today’s small cells, which have limited power budgets and often are powered using Power over Ethernet (PoE) technology. Given that the DSPLL integrates all PLL and power supply regulation elements on-chip, the Si5380 device delivers high board-level noise immunity, integrated power supply noise rejection and consistent, repeatable phase noise performance across temperature.

While VCXO-based clock solutions often suffer from degraded spurious performance when subjected to vibration, the Si5380 device’s integrated DSPLL technology maintains spurious response regardless of the system environment. It guarantees low phase noise operation when locked to a high jitter input clock, ensuring that data converter performance is not degraded by external effects. The Si5380 generates 4G/LTE frequencies up to 1.47456 GHz and provides up to 12 independently configurable clocks, which can be used for clocking JESD204B-compliant data converters, FPGAs and other logic devices.

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