The System Management Interface Forum (SMIF) has announced the latest version of its System Management Bus (SMBus) specification. Version 3.0 is backwards compatible and incorporates a number of major revisions to ease implementation for users of the protocol, broaden performance capabilities to ensure compatibility with the latest topologies and harmonise the specification with the I ²C and Power Management Bus (PMBus) specifications.
SMBus is a two-wire interface through which system component chips and devices can communicate with each other and with the rest of the system. SMBus is designed to provide a control bus for system and power management related tasks and may be used instead of individual control lines to pass messages to and from devices. In addition to reducing pin counts and supporting a flexible and expandable environment, SMBus delivers a useful range of functionality such as saving states from a suspended event and the reporting of errors.
Recognising the ability of the latest processors and custom logic to work at greater speeds, the 100 kHz bus frequency offered by SMBus 2.0 is uprated with two further speeds of 400 kHz and 1 MHz in the newly announced version 3.0. The addition of these increased speeds has in turn necessitated the adjustment and re-organisation of high power electrical drive levels. A further update has seen the data hold time specification changed to match the I ²C specification. The decision to align this parameter recognises that most devices on the market manage data hold time in accordance with I ²C.
Version 3.0 also includes the removal of a specification for minimum immunity to noise on the clock and data lines as the SMIF Working Group found that no supplier of SMBus devices or system OEM using SMBus ever tested against the parameter. Other changes include the re-use of defunct special bus addresses (formerly reserved for ACCESS Bus host and ACCESS Bus default address) for the zone