Mentor has addressed what it sees an issue of information exchange between design teams working at the interfaces between the physical aspects of integrated circuit/ASIC pinout; and the design and optimisation of custom IC packages; and the process of entering that package and pinout into the PCB place-and-route process. New packaging techniques – stacked dice, through-silicon vias and very hihg bump/pin counts – are forcing change, Mentor says.
There is necessarily a great deal of data that can be fed both forwards and backwards along that chain. An initial IC die-bump layout may call for a very complex pin assignment and interposer design within the IC’s package; looking a the constraints of the package design can generate feedback to the the IC pin placement that can subsequently simplify and cut costs in the package design. Similarly, an initial pin assignment on the package might demand a very complex routing escape pattern; a well-informed revision could simplify the board place-and-route, and save layers and costs. Where a change is necessary, it feeds back the required information to invoke a fresh run of an analysis tool, for example in areas such as signal integrity or thermal design
Mentor’s introduction addresses these “domain boundaries”. It does not link, in an active, “live windows” sense, the EDA packages used in each domain; but it facilitates extracting from each, just the data that is needed to pass key design information and constraints up and down the chain – automating a process that already takes place but with (sometimes cumbersome) manual and simple (e.g. spreadsheet) tools. It employs standardised data formats already established for exchange of data, and Mentor says it is vendor-agnostic in respect of any of the design tools used.
The Package Integrator solution automates planning, assembly and optimisation of complex multi-die packages. It incorporates a virtual die model concept for true IC-to-package co-optimisation. In support of early marketing-level studies for a proposed new