SoC IP for safety-compliant automotive systems

October 17, 2013 // By Graham Prophet
Synopsys has introduced an ARC EM SEP Processor in its DesignWare IP range for safety compliant automotive systems; it has integrated safety features and ASIL D-ready compiler to speed development of ISO 26262-compliant SoC designs

Synopsys' DesignWare ARC EM SEP (Safety Enhancement Package) Processor core for automotive safety compliant applications builds a 32-bit ARC EM SEP processor based on the efficient ARC EM4 core. It clocks at up to 300 MHz and power consumption is as low as 16 mW/MHz on typical 65nm low power silicon processes. It has integrated hardware safety features that enable ASIL D compliance in support of the ISO 26262 standard.

The DesignWare ARC MetaWare Compiler helps software developers accelerate the development of ISO 26262-compliant code and is undergoing ASIL D readiness certification by SGS-TÜV Saar, a leading independent safety certification company. The combination of a safety-enhanced processor and compiler suits the ARC EM SEP core for systems-on-chip (SoCs) designed for embedded automotive applications such as movement and acceleration sensors, advanced driver assistance systems and electric power steering.

The ARC EM SEP core is configurable to meet the unique performance, power and area requirements of each target application. Giving designers the ability to define custom instructions facilitates the integration of proprietary hardware accelerators that improve application-specific performance while reducing power consumption and the amount of memory required critical requirements in embedded automotive designs. The EM SEP processor integrates hardware safety features including ECC for single-bit error correction and double-bit error detection, and parity protection for single-bit error detection on closely coupled memories. To minimise system-level latencies and silicon area, SoC peripherals can be directly mapped to the CPU to enable single cycle access. Native ARM AMBA, AHB, AHB-Lite and BVCI standard interfaces are configurable for 32-bit or 64-bit transactions to optimise system throughput. Support for ARC EM SEP in Synopsys’ Virtualizer virtual prototyping environment allows for seamless integration with tools such as Mathworks’ Simulink, Vector’s CANoe and Synopsys’ Saber to enable virtual hardware-in-the-loop (HIL) simulation and fault testing.

The DesignWare ARC MetaWare Compiler and accompanying safety documentation help developers of safety critical systems fulfill the requirements of the ISO 26262 standard.