SoC test engineers, the EDA vendor says, have become used to an upper limit on text compression - the factor by which (in broad terms) the extent to which test patterns prepared for production can be reduced compared to a one-at-a-time accessing of all of the scan chains formed when the target device is placed in test mode. This factor has been accepted at [around] 100; now, Cadence says its latest code can extent that to 400, shortening text times. Test compression and decompression has conventionally been a combinational process; Modus adds [some] registers and a degree of combinational logic. Although this extends the data injected into each scan chain, a higher level of compression is enabled, with overall benefit.
The software also brings a new approach to adding the wiring (which must be inserted into the chip’s metallisation layers) that is needed to give the scan chain access in testing. Modes takes a more chip-wide view of the logic when creating that interconnect; and it uses a grid-based approach to laying those wired down. The result is a less congested, more manufacturable physical layout that has less impact on the DFT (design for text) insertion steps.
Overall the impact of DFT at synthesis stage is reduced; chip time on the tester is cut; and/or the added test-structure wire length is reduced – all without impacting test coverage.
- 2D compression: Scan compression logic forms a physically-aware two-dimensional grid across the chip floorplan, enabling higher compression ratios with reduced wirelength. At 100X compression ratios, wirelength for 2D compression can be up to 2.6X smaller than current industry scan compression architectures.
- Elastic compression: Registers embedded in the decompression logic enable fault coverage to be maintained at compression ratios beyond 400X by controlling care bits sequentially across multiple scan cycles during automatic test pattern generation (ATPG).
- Embedded memory bus support: A shared test access bus can be inserted