SoC/IP: on-chip memory test and repair for embedded flash

October 21, 2014 // By Graham Prophet
Synopsys’ DesignWare STAR Memory System for embedded flash reduces test cost and enables in-field diagnostics for IoT and automotive SoCs

DesignWare STAR Memory System for Embedded Flash is, Synopsys says, the EDA sector's first integrated memory test and repair solution with test algorithms optimised for on-chip embedded flash memories. The DesignWare STAR Memory System is an automated pre- and post-silicon memory test, diagnostic and repair solution that enables designers to improve test coverage, reduce design time, lower test costs and maximise manufacturing yield. The STAR Memory System for Embedded Flash is a built in self test (BIST) solution that tests for the failure mechanisms associated with embedded flash memories, reducing overall integration time and cutting associated test costs by 20% compared to external solutions. Embedded flash memories are increasingly used with microcontrollers in systems-on-chip (SoCs) for Internet of Things (IoT) wearables, smart appliances and automotive safety systems, which have stringent cost and reliability requirements.

“Synopsys’ DesignWare STAR Memory System for Embedded Flash is a valuable product for chip designers utilising our highly popular 55 nanometer process, which has already been widely adopted for numerous IoT applications,” said Shih Chin Lin, senior director of IP development and design support division at UMC. “Designers who are taking advantage of our 55 nanometer eFlash process will find that the post silicon debug and analysis capabilities of Synopsys’ Yield Accelerator and Silicon Browser will make designers’ product characterisation and validation efforts even more efficient.”

The STAR Memory System for Embedded Flash offers in-field diagnostic capabilities to identify issues during system operation. With these capabilities, memory issues can be diagnosed even after the devices have shipped to the end customer.

The STAR Memory System allows hierarchical generation and verification of the test and repair IP to be inserted into the SoC while maintaining the original design hierarchy. This can reduce integration effort and SoC development time by allowing reuse of existing design constraints and configuration files. Additionally, the post silicon Yield Accelerator and Silicon Browser features can reduce the time required for silicon bring-up and