Soft IP core handles HDLC/SDLC transmission for MCUs

December 03, 2013 // By Graham Prophet
Digital Core Design (Poland) has introduced the DHDLC soft IP Core, designed to control HDLC/SDLC transmission frame and optimised for a variety of 8, 16 and 32-bit MCUs. As with other DCD IP Cores, the DHDLC is a technology independent design, therefore can be implemented in both ASIC and FPGA.

The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, for 8-, 16- or 32-bit microcontrollers, relieving the processor of time spent for handling HDLC/SDLC features, such as bit stuffing, address recognition and CRC computation. To enable greater productivity, DHDLC has a FIFO buffer for both receiver and transmitter. Configurable core parameters and adjustable CPU interface are essential in this project.

The DHDLC IP Core is fully synchronous with a single clock domain design. All parameters are configurable by CPU, but there is also an another option; you can set all the parameters by modification constants in a source file, so there is no need to waste silicon resources for unused features and constant settings. Features include;

Two separate receiver and transmitter interfaces.

Two separate, configurable FIFO buffers for receiver and transmitter

Bit stuffing and unstuffing

Address recognition for receiver and address insertion for transmitter

Two or one byte address field

RC-16 and CRC-32 computation and checking

Collision detect

Byte alignment error detection

Programmable number of bits for idle detection

NRZI coding support

Shared flags, shared zeros support

Pad fill with flags option

Transmitter clock generation

8-bit, 16-bit, 32-bit CPU interface

Interrupt output for handling control flags and FIFOs’ filling

Configurable core parameters

DCD: http://dcd.pl/ipcore/670/dhdlc/