The company claims it can build a multicore processor where hardware orchestration logic allows multiple CPU cores to act as one, significantly improving instruction per cycle (IPC) performance over a single CPU core and allowing multicore processors to perform significantly better on single-threaded code.
The company has built a multi-national team, raised $175 million and is now close to demonstrating the first real products using its VISC technology. Soft Machine’s business model is flexible – offering a mix of both chips and licensable CPU IP.
The company’s first test silicon was built in late 2014 in a 28nm process. The details of the original test chip were reported back in 2014. The original demo didn’t silence the skeptics, but was enough to convince a number of investors to put more money in Soft Machines.
This year the company plans to tape out an SoC code named Mojave in a 16nm FinFET process based on a core named Shasta. The company also revealed an ambitious roadmap at The Linley Group Processor Conference in 2015 to deliver a new CPU and SoC every year for the next three years.
While the original 28nm proof-of-concept design was 32-bit, the new Shasta CPU emulates the 64-bit ARMv8 instruction set. Shasta includes two physical cores and can support one to two virtual CPUs. Future versions will support up to four physical cores.
The company’s stated goals are to deliver up to 2.5x performance improvement at the same power, or up to 4x energy advantage at the same performance compared with a standard ARM core. The comparison is of a present day ARM CPU with a future four core VISC CPU called Tahoe, schedule to ship in 2018.
Soft Machines recently updated its simulated performance numbers with comparisons to Apple’s A9X and Intel’s Skylake shown in the figure below. The company doesn’t have physical Shasta-based chips for testing, so its data was from simulations. Actual Shasta core RTL is scheduled to be released mid-2016 and the Mojave SoC tape out is expected in Q3 of 2016.
For the sake of an apples-to-apples comparison in its performance charts, Soft Machines normalized the processor configurations (cache sizes) between the ARM Cortex-A72, Apple A9X, Intel Skylake, and its VISC cores. This does not mean that the VISC cores will be configured exactly this way with regard to cache size.
The numbers look impressive as the single-threaded SPEC benchmark code sees a significant performance jump of roughly 40% even over high IPC processors like the A9X and Skylake. With that said, the SPEC code is staticly compiled and easy to optimize for. The tougher task for VISC will be dynamic code like Java. In addition, multicore benchmarks may not benefit as much from the dynamic workload balancing.