Spacecraft data handling using ARM-based processors

October 03, 2016 // By Rajan Bedi, SpaceChips
Earlier this year I attended ESA and NASA FPGA conferences, SEFUW and MAPLD respectively, and one topic which we discussed was the need for a small, low-power, high performing MCU to replace larger, more dissipative FPGAs. For localised control and processing, such as sensor TT&C (telemetry, tracking, and command) or digital control of a voltage regulator, a dedicated MCU would offer a more efficient CPU/DSP option.

Could the solution lie within our cellular phones (smart and not so smart), our tablets, our cars, our IoT devices, and our wearables? Today, almost 90 billion ARM-based chips are being used globally and many of these contain multiple ARM cores. Currently there are over 450 ARM licensees worldwide.


The ubiquitous ARM architecture offers small, low-power, high-performance cores, many of which are being used in safety-critical applications, such as car braking systems, power steering, self-driving vehicles, aircraft, medical, railway and industrial control sub-systems, conforming to fail-safe standards including ISO 26262, IEC 61508, DO-254, DO-178, IEC 62304, IEC 61511/13, IEC 62061, and ISO 13849.


Given that our lives depend on the reliability of ARM-based fail-safe systems every day, could the space industry also benefit from the performance, power, size, ease of use, and accessibility benefits of the ARM architecture? There is a huge, tried and tested ecosystem available to enable developers to build reliable control and DSP embedded applications, e.g. toolchains certified to TÜV SÜD. For safety-critical applications, exception handling is very short and deterministic, and two cores can be lock-stepped to provide redundancy. Further risk mitigation can be implemented at the SoC and system level.


There are a number of options available to allow the space industry to exploit the advantages of ARM's, small, low-power, high-performance architecture:


- Several space-grade foundries have licensed the ARM architecture and offer this IP as part of their Hi-REL, ASIC design flow, e.g. ST Microelectronics sells many ARM cores commercially and can harden these for satellite customers baselining its 65 nm, space-grade ASICs.

- Satellite OEMs can instantiate ARM IP within FPGAs, e.g. users of Microsemi's ProASIC3 and RTG4 have access to a soft (not placed and routed) 16/32-bit, 60 MHz, ARMv6-M, Cortex-M1 core , which can be implemented using 4,353 logic tiles. Future space-grade FPGAs discussed at SEFUW and MAPLD will allow dual, 32-bit, ARMv7-R, Cortex-R5 cores up to