Asked why, given the vast resources that have been poured into semiconductor device development over many years, it should fall to a third-party IP company to offer a power-saving innovation in something so fundamental as the basic transistor, a SuVolta spokesman offered a simple explanation. Almost all [conventional] device development has been fundamentally aimed at increasing performance, and low-power variants have been derived from those devices. SuVolta says its approach has been to carry out basic transistor development with low-power as the primary aim. You can trade-off that gain to see faster speeds at equivalent power, the company adds.
Now, the company says that its claims have been validated by with Fujitsu's implementation of an ARM processor core in 65-nm technology using its transistors, yielding significant processor speed gains with associated power reduction in a Cortex-M0 processor. The ARM Cortex-M series processor was manufactured with SuVolta’s Deeply Depleted Channel (DDC) technology on a 65nm bulk planar CMOS DDC process. With SuVolta’s transistor technology, designers are able to significantly reduce power or dramatically improve performance, depending upon design requirements.
When compared to an identical ARM Cortex-M0 processor manufactured in the conventional 65nm process, with a 1.2V supply voltage, the DDC transistor-based ARM implementation operating at 0.9V demonstrates the following benefits:
50% lower total power consumption at matched 350 MHz operating speed.
35% increased operating speed (performance) at matched power.
55% increased operating speed when operated at matched supply voltage.
“We’ve now validated the benefits of the DDC technology in a complex SoC, by combining the ARM Cortex-M0 CPUs with SRAM instances and various analogue components,” explained David Kidd, senior director, digital design at SuVolta. “The results speak for themselves – power-performance optimized CPU cores, with results that hold across process corners and temperature, plus, SRAMs with 150 mV lower minimum operating voltage, 50% less leakage power at matched SRAM read current, and more than 5x less leakage power in retention mode.”