ST, ARM, Cadence to boost transaction-level ESL tool operability

July 30, 2013 // By Graham Prophet
STMicroelectronics, ARM and Cadence are aiming to improve tool and model interoperability with three joint contributions to the Accellera Systems Initiative; proposing interfaces for Interrupt Modelling, Register Introspection and Modelling of Memory Maps will enable third-party model and tools markets and make early virtual prototypes more effective.

The three companies are making three new contributions to the SystemC Language Working Group of the Accellera Systems Initiative. This collaboration will further increase model and tool interoperability for electronic system-level (ESL) design at the transaction-level.

With these contributions, ST, ARM and Cadence expect the integration of SystemC models in virtual prototypes will be significantly improved for all users, enabling the models’ quick and efficient deployment. In addition, standard interfaces between models and tools will extend hardware/software integration and debug capabilities using appropriate tools.

The joint work includes new interfaces for interrupt modelling, which allow seamless integration of models from different companies; application programming interfaces for register introspection that enable tool interoperability to seamlessly display and update register values; and new approaches for memory-map modelling that improve users’ productivity during debugging of virtual platforms for hardware/software multicore systems. The contributions consist of fully working application programming interfaces (API) and implementations, as well as documentation and examples, released under an Apache 2.0 open-source license and available online at http://forums.accellera.org/files/

“These new interfaces are crucial to strengthening the ESL ecosystem. As a step towards interoperability driven by ST, ARM and Cadence, these proposed standards dramatically reduce risks and efforts associated with the integration of virtual prototypes. Eliminating the need for adapters will increase virtual prototype simulation performances, enable sooner and faster hardware-software integration, and therefore improve product time-to-market,” said Philippe Magarshack, executive vice president, Design Enablement & Services, STMicroelectronics.

“Cadence has worked closely with ST, ARM and other partners to develop these open standards proposals,” said Stan Krolikoski, distinguished engineer, Cadence. “Adoption of these proposed standard interfaces in virtual prototyping solutions will enable the expansion of the ESL ecosystem and provide added value through interoperability to users.”

“The Accellera TLM 2 standard has been very important in enabling an ecosystem of models that can be integrated into SystemC virtual prototypes,” said John Goodenough, vice president of Design Technology and Automation, ARM. “By