The silicon-verified process technology claims to deliver 30% higher speed and up to 50% improvement in power.
The announcement confirms ST’s ability to provide its planar fully-depleted technology from the 28 nm technology node, essential for embedded processors in multimedia and portable applications that can meet the industry’s highest performance and lowest power demands vital to deliver all the graphics, multimedia and high-speed broadband connectivity without sacrificing battery life.
The FD-SOI Technology Platform encompasses the availability of a feature-complete and silicon-verified Design Platform, including the full set of foundation libraries (std-cells, memory generators, I/Os), AMS IPs and high speed interfaces), and a design flow ideally suited for developing high-speed and energy-efficient devices.
ST’s FD-SOI technology has already been selected by ST-Ericsson for use in its future mobile platforms, which will enable enhanced performance with lower power consumption than conventional technologies.
“ST has a long history in pioneering new solutions in both product and technology. By bringing FD-SOI technology to manufacturing readiness, ST is again positioning itself as an innovator and leader in semiconductor technology development and manufacturing,” said Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, and Chief Technology and Manufacturing Officer of STMicroelectronics. “Post-processing wafer testing has allowed us to prove the significant performance and power advantages of FD-SOI over conventional technologies, building a cost-effective industrial solution that is available from the 28nm node. Measurements on a multi-core subsystem in an ST-Ericsson NovaThor ModAp platform, with a maximum frequency exceeding 2.5 Ghz and delivering 800 MHz at 0.6 V, are confirming expectations and demonstrating the great flexibility of the technology and the extended voltage range exploitable through DVFS (Dynamic Voltage and Frequency Scaling).”
As important as its success in manufacturing, ST has found porting Libraries and Physical IPs from 28 nm Bulk CMOS to 28 nm FD-SOI to be straightforward, and the process of designing digital SoCs with conventional CAD tools and methods in FD-SOI to be identical