Sub-20-nm FinFETs, and 3D chip technology, reach “reference” status

September 18, 2013 // By Graham Prophet
Further signs that the semiconductor industry is pressing ahead with geometries of under 20-nm, and with more advanced device packing techniques, comes with an announcement from TSMC that it and its partners are delivering 16FinFET and 3D IC reference flows

The three silicon-validated Reference Flows within the Open Innovation Platform (OIP) enable 16FinFET systems-on-chip (SoC) designs and 3D chip stacking packages. Electronic Design Automation (EDA) vendors collaborated with TSMC to develop and validate all these flows through multiple silicon test vehicles.

The new Reference Flows are:

  1. TSMC’s 16FinFET Digital Reference Flow, providing technology support to address post-planar design challenges including extraction, quantised pitch placement, low-Vdd operation, electromigration, and power management;

  2. 2. The 16FinFET Custom Design Reference Flow, offering full custom transistor-level design and verification including analogue, mixed-signal, custom digital and memory; and

  3. The 3D IC Reference Flow, addressing emerging vertical integration challenges with true 3D stacking.

“These Reference Flows give designers immediate access to TSMC’s 16FinFET technology and pave the way to 3D IC Through-Transistor-Stacking (TTS) technology,” said TSMC Vice President of R&D, Dr. Cliff Hou.

The 16FinFET Digital Reference Flow uses the ARM Cortex-A15 multicore processor as a validation vehicle for certification. It helps designers adopt the new technology by addressing FinFET-structure-related challenges of complex 3D Resistance Capacitance (RC) modelling and quantised device width. In addition, the flow provides methodologies for boosting power, performance and area (PPA) in 16nm, including low-voltage operation analysis, high-resistance layer routing optimisation for interconnect resistance minimisation, Path-Based Analysis and Graph-Based Analysis correlation to improve timing closure in Automatic Place and Route (APR).

The 16FinFET Custom Design Reference Flow enables custom design by addressing the growing complexity of 16FinFET process effects and provides methodologies for design compliance in 16nm manufacturing and reliability.

The 3D IC process produces silicon scaling, power and performance benefits by integrating multiple components on a single device. TSMC’s 3D IC Reference Flow addresses emerging integration challenges through 3D stacking. Key features include Through-Transistor-Stacking (TTS) technology; Through Silicon Via (TSV)/microbump and back-side metal routing; TSV-to-TSV coupling extraction.

OIP promotes innovation for the semiconductor design community and ecosystem partners based on TSMC’s complete technology portfolio. OIP includes a set of ecosystem interfaces and