SynchE/IEEE1588-2008 timing devices for infrastructure and mobile backhaul

August 12, 2013 // By Graham Prophet
Microsemi has announced the highest density family of single-chip timing card devices with support for both Synchronous Ethernet (SyncE) and IEEE 1588-2008 packet networks including 4G and LTE applications.

The highly integrated ZL30361, ZL30362 and ZL30363 provide all of the key elements required for wireless network synchronisation including support for phase and frequency. The devices are being designed into wireless backhaul products where phase synchronisation performance is crucial. These timing devices provide the highest level of flexibility, smallest footprint (13 x 13mm) and lowest cost compared to alternative solutions. Key features include the availability of up to four independent timing channels; each channel can be configured to support any electrical or packet mode of operation. This allows for the simultaneous support for GPS, SyncE and IEEE1588-2008 timing. As a result, these devices can be used to enhance or to replace GPS timing in wireless infrastructure at a lower cost.

“Our new SyncE/IEEE1588 solutions provide customers with a highly compelling value proposition and very flexible architecture as evidenced by several product design-ins already in development by leading telecom companies," said Maamoun Seido, vice president of Microsemi's Timing Products group.

SyncE and IEEE 1588-2008 technologies allow carriers to improve synchronisation and performance in packet-switching networks including the fast-growing 4G and LTE segment.

This SyncE/IEEE1588 timing solutions features multiple digital phase locked loops (DPLL) tailored for wireless infrastructure and mobile backhaul networks. The ZL30362 has four highly programmable multi-function DPLLs, coupled with four independent synthesisers capable of generating multiple independent frequencies to directly drive both 1 Gigabit Ethernet (GbE) and 10GbE physical layers (PHYs). The ZL30361 and ZL30363 timing card devices feature single and dual multi-function DPLLs, coupled with three and four high performance synthesisers, respectively.

The ZL30361, ZL30362 and ZL30363 are based on Microsemi's two stage ClockCenter architecture which supports any rate-to-any rate frequency translation from 1 Hz to 750 MHz, including GPS 1 pulse per second (pps) input. Microsemi has added standards-compliant IEEE 1588-2008 protocol with Clock Recovery Servo to the devices, which are Microsemi’s third-generation packet timing solution.

The ZL30362 is the only timing device available today that meets