Synopsys’ Verification Compiler spans complete verification flow for SoC

March 05, 2014 // By Graham Prophet
Next generation verification technologies, including static and formal verification, provide a five-times performance improvement, Synopsys claims.

Native integration of simulation, static and formal verification, verification IP (VIP), debug, and coverage technologies into a single product boosts performance and productivity; advanced SoC debug capabilities build on the Verdi3 debug platform enhance debug efficiency. The methodology includes complete low power verification with native low power simulation, X-propagation simulation, next generation low power static checking and low power formal verification.

A broad portfolio of verification IP, including ARM AMBA 4 AXI and AMBA 5 CHI interconnect, Ethernet, MIPI, PCIe and more, are integrated with simulation and debug.

Verification Compiler is a product that Synopsys has structured for system on chip (SoC) verification technology and verification roadmaps. It is a complete portfolio of integrated verification technologies that include advanced debug, static and formal verification, simulation, verification IP and coverage closure. Together these technologies offer a five-times performance improvement and a substantial increase in debug efficiency, enabling SoC design and verification teams to create a complete functional verification flow with a single product. The combination of next generation technologies, integrated flows and a unique concurrent verification licensing model enables Verification Compiler to deliver a claimed three-times gain productivity overall – directly addressing the growing SoC time to market challenge.

Advanced SoC development faces exponential growth in verification complexity, new power efficiency requirements, increasing software content and tougher time-to-market pressures. Achieving verification closure for these complex SoCs requires a broad set of technologies including advanced debug, static and formal verification, low-power verification, verification IP and coverage closure.

To address this challenging verification landscape, Verification Compiler features a comprehensive set of next-generation technologies, including formal verification, SoC connectivity checking, SoC-scale clock domain crossing (CDC) checking, X-propagation simulation, native low power simulation, and advanced verification planning and management. Verification Compiler also includes the entire portfolio of Synopsys’ verification IP, including the corresponding test suites, all integrated for advanced debug and high-performance simulation. By integrating these technologies in a single product, Verification Compiler enables SoC