The continued scaling of logic transistors and memory cells to smaller and smaller dimensions requires new materials and architectures, which increase chip complexity and extend process development time for semiconductor manufacturers. The Synopsys TCAD tools have proven very effective in helping to reduce the number of engineering wafers needed to develop new technologies, acting both as a prototyping tool to explore new device architectures before a process is defined and as an engineering tool for process integration and optimization. In this collaboration, Applied Materials will supply critical film properties and device characterization data from its advanced process systems to Synopsys, thereby enabling the development of models using Synopsys' Sentaurus TCAD tool suite.
The collaboration encompasses front-end-of-line (FEOL) processing, including process, topography and device simulation, and back-end-of-line (BEOL) reliability, including interconnect simulation. Previously, the two companies worked together on Silicon Germanium (SiGe) source/drain stressors where Synopsys TCAD models were calibrated with epitaxial films grown in an Applied Materials system. The companies have also collaborated on calibrating multiple ion implant schemes and through-silicon via (TSV) development.
"TCAD modeling has been essential for the development of 3D FinFET and memory technologies," said Howard Ko, senior vice president and general manager of the Silicon Engineering Group at Synopsys. "The combination of Applied Materials' equipment and Synopsys' TCAD software will enable process engineers to continue scaling logic and memory devices. This collaboration combines the strengths of both companies and will provide leading-edge semiconductor companies tools to tackle the challenges and reduce the cost of technology development."