Synopsys’ pattern generation for IC test offers ‘days to hours’ reduction

July 14, 2016 // By Graham Prophet
Synopsys’ TetraMAX II software, generting test patterns for large scale IC and SoC designs, incorporates new ATPG engines reduce to test cost and pattern count by 25%, and yield order-of-magnitude faster runtimes.

Faster ATPG ensures, Synopsys says, on-time availability of patterns for testing first silicon samples; the pattern reduction enables designers to reduce test cost or alternatively increase test quality at the same cost per design requirements; and re-use of proven interfaces enables risk-free, easy deployment.


TetraMAX II is built on new test generation, fault simulation and diagnosis engines that are fast, memory efficient, optimized for generating patterns and capable of executing fine-grained multithreading of the ATPG and diagnosis processes. Memory efficiency in TetraMAX II enables utilization of all server cores regardless of design size, in contrast to previous solutions that are limited by high memory usage. The reuse of production proven design modelling and rule checking infrastructure, as well as user and tool interfaces, ensures designers can deploy TetraMAX II risk-free on the most challenging designs. TetraMAX II utilizes established links with Synopsys Galaxy Design Platform tools, such as DFTMAX, PrimeTime timing analysis and StarRC extraction tool, and other Synopsys tools, including Yield Explorer yield management and Verdi debug tools, to deliver the highest quality test and the fastest, most productive flows.


Synopsys has a user endorsement from STMicroelectronics, quoted as seeing significantly faster test pattern generation runtime and reduced number of patterns with TetraMAX II ATPG. On a multi-million-gate FD-SOI SoC design, TetraMAX II demonstrated an order of magnitude speedup in runtime and significant test-pattern-count reduction without impacting test coverage.


ISO 26262 certification

Synopsys has also disclosed that the TetraMAX II ATPG code has been certified for ISO 26262 (automotive functional safety). The tool certification accelerates ISO 26262 functional safety qualification for automotive ICs up to the most stringent safety requirements for ASIL D, and enables automotive IC design teams to accelerate their manufacturing test development process.

SGS-TÜV Saar GmbH, an independent accredited assessor, formally certified TetraMAX II, following an in-depth functional safety tool qualification. Certification provides designers the highest level of confidence in the use of