Synopsys renews layout tools for analogue, custom ICs in FinFET era

March 31, 2016 // By Graham Prophet
In contrast to high-density logic designs, layout of custom, analogue-mixed-signal ICs remains largely a manual process – with assistance from EDA tools. The advent of FinFET processes necessitates, Synopsys says, a new generation of software.

The company observes that, while some observers had previously speculated that FinFET and 14/16 nm processes – and smaller – would remain the province of high-end digital designs alone; and that AMS and custom designs would “stick” at older process nodes, this is no more true now than it has ever been, and AMS design is migrating to FinFET processes.

 

This, according to the company’s David Reed, changes the detail work of analogue layout significantly. A single transistor, depending on the parametric performance required of it, becomes an array of fins – for example. However, Reed notes that despite the very different physical context, the intuitive understanding of circuit topology and floorplan that the analogue designer has, still transfers well to the FinFET era. In the immediately prior generations of custom layout tools, there had been a move to drive analogue layout with a more scripted, “logic-like” approach. This, Reed comments, has been a limited success and this new release of tools – Custom Compiler – in some ways represents a return to earlier techniques. Continuous, real-time parameter extraction and simulation guides the designer throughout the process.

 

Synopsys’ Custom Compiler is therefore pitched as “ Visually-Assisted Automation” with a number of point tools that are not full automation but are configured as “assistants”. Template Assistants help designers reuse existing custom layout know-how; In-Design Assistants reduce iterations with native design rule checks and parasitic extraction; Layout Assistants speed up layout tasks with user-guided placement and routing; and Co-Design Assistants unify custom and digital flow to accelerate mixed-signal IC design.

 

Custom Compiler, says the company, closes the FinFET productivity gap by shortening custom design tasks from days to hours. To bring new levels of productivity to FinFET layout, Synopsys has taken a fresh approach to custom design by developing visually-assisted automation technologies that speed up common design tasks, reduce iterations and enable reuse. Developed through close collaboration with leading