Synopsys unveils 3D-IC initiative for designing stacked multi-die systems

March 27, 2012 // By Julien Happich
Synopsys unveiled its initiative to accelerate the design of stacked multiple-die silicon systems using 3D-IC integration to meet the requirements of faster and smaller electronic products that consume less power.

As part of its 3D-IC initiative, the company is working closely with leading IC design and manufacturing companies to deliver a comprehensive EDA solution, including enhanced versions of its IC implementation and circuit simulation products. 3D-IC technology complements conventional transistor scaling to enable designers to achieve higher levels of integration by allowing multiple die to be stacked vertically, or in a side by side “2.5D” configuration on a silicon interposer.

Synopsys' 3D-IC initiative begins at the semiconductor device level. Multi-die stacks incorporate different materials, often bonded together, with varying coefficients of thermal expansion (CTE). Any temperature change causes material stress due to thermal mismatch, leading to silicon deformation and affecting transistor performance. Furthermore, TSVs, microbumps and other solder bumps produce a permanent stress in the zone around them. Synopsys’ Sentaurus Interconnect TCAD tool analyses these effects and models the TSVs in the die stacks, enabling performance and reliability optimisation. Semiconductor companies, such as foundries, use modeling results to create design rules specific to 3D-IC integration to ensure manufacturability and reliability.

The tools include:

DFTMAX test automation: design for test for stacked die and TSV

DesignWare STAR Memory System IP: integrated memory test, diagnostic and repair solution

IC Compiler: place and route support, including TSV, microbump, silicon interposer redistribution layer (RDL) and signal routing, power mesh creation and interconnect checks

StarRC Ultra parasitic extraction: support for TSV, microbump, interposer RDL and signal routing metal

HSPICE and CustomSim circuit simulation: multi-die interconnect analysis

PrimeRail: IR-drop and EM analysis

IC Validator: DRC for microbumps and TSVs, LVS connectivity checking between stacked die

Galaxy Custom Designer implementation solution: specialised custom edits to silicon interposer RDL, signal routing and power mesh

Sentaurus Interconnect: thermo-mechanical stress analysis to evaluate the impact of TSVs and microbumps used in multi-die stacks

The Synopsys 3D-IC solution is available now in beta and is expected to be in production in calendar Q2 of 2012.

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