Synopsys updates IC place-&-route flagship; IC Compiler II

March 25, 2014 // By Graham Prophet
A new generation of the company’s physical-design place-and-route tool for complex SoC designs in leading-edge silicon processes claims as much as a 10-fold increase in physical design throughput.

IC Compiler, Synopsys says, is the biggest single product in its overall offering: in looking to renew it, the question the company asked was, “what more [in P&R] can we do?”. Built from the ground up on a completely new, multi-threaded infrastructure, IC Compiler II introduces ultra-high-capacity design planning, unique clock-building technology and advanced global-analytical closure techniques. As a major step from the existing IC Compiler, the new tool will be offered in parallel; the existing suite will continue to be supported and developed. It will be most attractive to the leading-edge nodes; Sysnopsys says that its collaborators who have helped develop it have employed it at 28 nm and below, “...and one at 45 nm.” Users will migrate from IC compiler, “according to design need and at a time of their choosing.”

However, Synopsys sees many of its customers opting to stay at more mature process nodes, for longer, as the increased complexity of moving to a new node can result in a diminshing-returns effect. If market advantage cannot be so easily gained by technology progression, then the need for effective tools to, “get chips out” becomes more prominent.

The claim of 10-times faster throughput is based on separate speed-ups of 10x in design planning, 5x in implementation, and doubled capacity. This enables, Synopsys says, a more speculative approach to IC layout, with more freedom for designers and architects to try out design variants.

next; IC Compiler II structure