Synthesiser has ultra-low phase jitter for 100G serial data communications

November 24, 2014 // By Graham Prophet
IDT’s 8T49NS010 synthesiser has 10 outputs with 86 fsec RMS phase jitter, for 40GE and 100GE applications

Integrated Device Technology has a high-performance synthesiser with ultra-low phase jitter for reducing bit error rates in serial data communications systems. The 8T49NS010 with an integrated fanout buffer/divider delivers high-performance clocks, suitable for 40GE and 100GE telecommunications and networking systems.

The 10-output synthesiser provides a high-frequency clock with 86 fsec RMS phase jitter over the standard 12 kHz to 20 MHz integration range. The 8T49NS010 has an integrated fanout buffer, removing the issues of additive phase jitter and noise coupling from oscillator to fanout buffer. The chip supports programmable configurations and output levels.

The 8T49NS010 is configurable through an I²C serial interface and operates over an industrial temperature range. In addition to output power-down, it supports two logic levels for its differential outputs; the first provides an LVPECL output level with 750 mV typical swing, while the second provides a similar swing and output level with no external DC termination. The device uses an external fundamental mode crystal, alleviating the expense and availability issues associated with high-end oscillators. Specified noise floor is -161 dBc/Hz.