System Builder design tool for Microsemi's SmartFusion2 SoC FPGA designs

June 17, 2013 // By Graham Prophet
Microsemi's SmartFusion2 SoC FPGA has an upgrade to its design tools with System Builder, a new design tool within the Libero System-on-Chip (SoC) Design Environment version 11.0 that is targeted at accelerating customer definition and implementation of ARM-based systems using SmartFusion2 SoC FPGAs.

“The System Builder tool significantly simplifies the design process for Microsemi’s SmartFusion2 SoC FPGAs in embedded system applications,” said Jim Davis, vice president of software and systems engineering at Microsemi. “As these devices have grown in complexity the architecture specification stage of the design has become increasingly error-prone. With System Builder the designer can quickly and easily define the desired system architecture via a high-level step-by-step process.”

Output from System Builder is automatically generated and correct-by-construction, thus eliminating the errors that are created when the architecture is specified ‘by hand’ as in more traditional tool flows. Additionally, software-oriented engineers can create an embedded architecture and begin code development on their own. This simplifies the adoption of SmartFusion2 devices and provides a much broader set of design engineers with access to SoC FPGA technology. The enhanced System Builder flow also enables Microsemi to support more customers with its internal design services team that offers digital or mixed signal design for custom functional blocks, Soft IP, firmware development and even complete designs.

System Builder users are guided step-by-step through each of the main SoC FPGA architecture blocks. The design process uses a high-level graphical interface that reacts to previous architecture selections and guides the user through the process of selecting options and configuring only the required embedded system blocks. The resulting system specification is automatically generated and correct–by-construction. It includes both the configuration and interconnects of the ARM processor and its related peripherals as well as other IP blocks implemented in the FPGA fabric. System Builder can also configure a growing set of IP blocks for high-performance interfaces including DDR2/DDR3/LPDDR memory controllers, and serial interfaces using 5Gbps SERDES for PCIe, XAUI (10 GbE) and SGMII. Additional fabric-based parameteried IP functions available within System Builder include I 2C, SPI, Timers, UARTs and PWM blocks. This resource of IP functions can be used to create application-specific SoCs, reducing time-to-market for the full range