System-level memory model library aids architecture evaluation

February 04, 2016 // By Graham Prophet
Mirabilis Design’s (Sunnyvale, California) VisualSim Memory modelling library contains all current and prior versions of DDR, LPDDR, HBM, SRAM, JEDEC-compliant memory controller and a generic memory controller. It is presented as the largest collection of memory models to evaluate bandwidth, read and write latency, and power consumed for different user cases.

System designers and architects can use this library to develop new memory sub-systems, explore new standards and algorithms, and optimise the memory access for their target application. The solution has been used to conduct trade-off between different speed/variations of DRAM, performance vs. power, and memory bandwidth efficiency. The library elements can be combined with the VisualSim architecture library to assemble a full system or SoC.

“Memory interface design and analysis is the biggest demand from our system-level customer base”, said Deepak Shankar, Founder of Mirabilis Design. “This library is a first of its kind and contains all the required models in one folder. Our customers are using these blocks to architect deterministic read/write latency and maximise battery life.”

VisualSim Memory can be used with VisualSim resource, behaviour and cycle-accurate modelling libraries to construct models, simulate and analyse the complete system or SoC. This library is used to validate proposal, conduct trade-off decisions, timing, throughput, arbitration algorithm, power consumption analysis, and study systems behavior with different configuration (single vs. dual channels, clock speed variations, addressing schemes, and controller algorithms).

- DRAM blocks available are DDR2, DDR3, DDR4, LPDDR2, LPDDR3, LPDDR4, and SRAM

- Storage blocks available are Flash and SSD

- New technology available are NVM, and HBM

- Memory controllers available are JEDEC-standard, Multi Port-Multi Channel, and generic.

- Statistical and Cycle-Accurate Cache available

- Memory controller and RAM blocks can be combined with the processor, RTOS, buses, interfaces, traffic generators and other architecture components to assemble the entire system.

- The modelled systems can be simulated for a variety of interface speeds, traffic rates, memory capacity, controller attributes, vendor-specific timing.

Pricing for the VisualSim Memory Modeling Library starts at $5,000; it requires VisualSim Architect to construct models and simulate. ( VisualSim Architect is a system-level modeling, simulation, and analysis environment with a wide-ranging set of libraries and application templates that significantly improve model construction and analysis time.) The product