Technology-independent IP builds a versatile I²C controller

March 05, 2015 // By Graham Prophet
Digital Core Design, IP Core provider and a System-on-Chip design laboratories from Poland, has introduced a soft IP Core, targeting I²C design needs.

The DI2CM core provides an interface between a microprocessor or microcontroller and the I²C bus. It can work as a master transmitter or master receiver - depending on a working mode, determined by the microcontroller. This universal solution is available with various system interface wrappers such as AMBA - APB Bus, Altera Avalon Bus, or Xilinx OPB Bus.

DCD comments that describing the I²C as a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many devices, is quite obvious, but the reality is that the I²C bus can be very confusing, and not only for the newcomers.

The DI2CM core provides an interface between a microprocessor or microcontroller and the I²C bus. It can work as a master transmitter or a master receiver, as determined by its working mode, set by the microprocessor or microcontroller. The DI2CM core incorporates all features required by the latest I²C specification, including clock synchronisation, clock stretch, arbitration, multi-master systems and high-speed transmission mode. The DI2CM IP Core has also been equipped with built-in timer, which allows operation for a wide range of clk frequencies.

DCD’s latest solution is a technology independent design, and as with the company’s other IP Cores, it can be implemented in a variety of process technologies.

Features include;

  • Conforms to the latest I²C specification

  • Master operation

  • Master transmitter

  • Master receiver

  • Support for all transmission speeds

  • Standard (up to 100 kb/sec)

  • Fast (up to 400 kb/sec)

  • Fast Plus (up to 1 Mb/sec)

  • High Speed (up to 3.4 Mb/sec)

  • Arbitration and clock synchronisation

  • Support for multi-master systems

  • Support for both 7-bit and 10-bit addressing formats on the I²C bus

  • Interrupt generation

  • Built-in 8-bit timer for data transfers speed adjustment

  • Host side interface dedicated for microprocessors/microcontrollers

  • User-defined timing (data setup, start setup, start hold, etc.)

  • Available system interface wrappers:

  • AMBA - APB Bus

  • Altera Avalon Bus

  • Xilinx OPB Bus

  • Fully synthesisable

  • Static synchronous design