Through-silicon-vias to split more chips: re-integration is the focus

January 27, 2015 // By Julien Happich
At the European 3D TSV summit which took place in Grenoble's Minatec centre in January 2015, all of the speakers seemed to agree on one thing: in many fields including the consumer market, 2.5D integration (through the use of interposers) is going to remain cost-competitive for a while with real 3D vertical integration.

And this could lead to major shifts in the electronics manufacturing landscape.

Barnett Silver, Senior Vice President & Principal at semiconductor consulting firm ATREG gave us his insight on the packaging and IC manufacturing markets.

The total costs for process and fab development has risen dramatically from one node to the next over the last decade, he notes, and only a handful of foundries will have the cash to stay in the race beyond the 14nm node, namely TSMC, Samsung and Intel. That makes OEMs and fabless companies overly reliant on very few foundry options, as rather captive customers. Hence the necessity for large OEMs to vertically re-integrate their strategic silicon supply chain.


Chip integration going full circle: source ATREG.



Silvers sees an inflection point coming over the next three years, when cash-rich OEMs such as Apple, Google or Amazon could invest more and more into foundries and IC packaging facilities to secure their supply chain, have better access to advanced nodes and reduce the risk of silicon allocation. Sitting at the negotiation table of many foundries and IDMs acquisitions/mergers, Silver said he had witnessed such large OEMs making bids (although unsuccessfully so far).

One way to counter TSMC’s unabated foundry market dominance would be for OEMs (Original Equipment Manufacturers) to acquire both OSATS (Outsourced Semiconductor Assembly and Test Services) and foundry shares and develop alternative manufacturing models, with varying levels of capital engagement, operating responsibility and ownership.

Such hybrid semiconductor manufacturing models, as Silver calls them, could include “Equity for Capacity”, where a semiconductor firm or OEM would invest in a fab to have a stake in the overall success of the fab (including guaranteed access to capacity), or more Cooperative (co-op) models, whereby a fab is co-owned and operated among multiple semiconductor firms (ensuring a proportional access to overall capacity while sharing the running expenses).


Advanced packaging will remain a clear differentiator and will drive re-integration: source ATREG.



“In this picture, packaging is essential, yet largely overlooked”, Silver notes, so he sees a convergence of OSATs and foundry services.

Later we learned from [analysts] Yole Développement that already in 2014, around 19% of overall semiconductor IC wafers were manufactured with packaging features (bumping, RDL, TSV, etc...) processed at the wafer-scale (with still a feature size gap between Silicon device and PCB processing for OSATS to play a role).

“I expect more Mergers & Acquisitions with foundries, OSATs and IDMs all fighting for the $51 billion chip assembly & test market. As the packaging gets more advanced, often at wafer-level, there will be re-integration and convergence between the front-end and the back-end”, Silver concluded.

While much progress has been made on TSVs, their resolution, depth, aspect ratio, they are still cost prohibitive for all but high-end applications including server memory or high performance computing. Although 2015 is regarded as the year of the 3D TSV (with several high bandwidth memories ramping up in volume), much of the debate at this year’s European 3D TSV summit was about when such full 3D architectures would compete in consumer applications, cost-wise, with 2.5D interposers. This uncertainty is an opportunity for OSATs to extend their offerings and fight off the foundries’ pretentions to do it all.

According to E. Jan Vardaman, President of semiconductor packaging consulting company TechSearch International Inc., although TSVs are largely used in sensors and MEMS, the yield issues but also the thermal challenges for stacking memory and logic together still make 3D TSV unattractive for consumer applications (a statement with which Qualcomm Technologies’ Senior Program Manager, Mustafa Badaroglu, would later agree).

Vardaman sees monolithic integration of logic and memory happening in 2018 at the earliest, while the price pressure on smartphones would make it difficult to adopt 3D TSVs for logic-on-logic stacking before 2019.