The original MSP designation, TI recalls, stood for “mixed-signal microcontroller” and the 32-bit parts follow that path with features such as a 14-bit ADC. TI has developed a customised process at 90 nm geometry, that it runs in its own fabs, to provide the performance/power characteristics it needs for these MCUs. The process has been characterised to run in an external fab if the need for a full second source arises.
The devices run at clock speeds of up to 48 MHz, achieving 95 µA/MHz in active power and 850 nA in standby power, and returning 3.41 on the EEMBC CoreMark benchmark. TI says this is the lowest power Cortex-M4F MCU implementation available anywhere; when deciding on a 32-bit core, the company says it considered a Cortex-M0+ but quickly determined that its process allowed the use of the higher-performance M4F with no power penalty. The MSP432 MCUs also deliver a best-in-class ULPBench (also by EEMBC) score of 167.4 – outperforming all other Cortex-M3 and -M4F MCUs, TI says.
TI uses is own flash memory on the chips, organised in banks that allow operate-from-one/erase-another. The process does not support FRAM, and TI’s FRAM MCUs continue on their own, separate path. As part of its support, TI provides a driver library – customer profiles for its prior devices showed this to be sufficiently popular that the company opted to place it in ROM on the 432 series, providing faster run-time operation.
An integrated DC/DC optimises power efficiency at high-speed operation, while an integrated LDO reduces overall system cost and design complexity. The 14-bit ADC operates at 1 Msample/sec and achieves and ENOB (effective number of bit) of 13.2: it consumes 375 µA at 1Msps. MSP432 MCUs include a selectable RAM retention feature that provides dedicated power to each of the eight RAM banks needed for an operation, so overall system power can be trimmed by 30 nA per bank. MSP432