The 32-nm asynchronous test chip, built using Tiempo's delay-insensitive technology, includes Tiempo's asynchronous 16-bit microcontroller (TAM16), and was functional through an extended voltage range in all the corners of the process, independent of the wafer position and observed process variability, the company said.
The chip was designed using ST's 32-nm design platform which now includes an asynchronous cell library jointly developed by CEA-Leti and Tiempo. The test chip was modeled in System Verilog and synthesized with Tiempo's asynchronous circuit compiler, then placed-and-routed using standard back-end tools.
Designers of traditional clocked circuits have to allow significant margins to ensure the chip will be functional, sometimes to the extent that for certain sub-circuits hardly any die area can be saved over the previous production node.
"Our clockless approach solves these issues as every chip operates at its optimal speed depending on silicon and manufacturing characteristics," said Serge Maginot, CEO of Tiempo, in a statement. Maginot said Tiempo would expand to more advanced nodes. He added that clockless circuits could also provide important feedback to developers for technology performance characterization and for calibration of EDA tools used for clocked digital design.
"The extreme simplicity of integrating the TAM16 microcontroller on an advanced CMOS process using industry-standard EDA tools has proven the robustness of Tiempo's design approach," said Robin Wilson, R&D design department manager at ST, in the same statement. "Furthermore TAM16 operates across a very wide voltage range, without any additional design effort."
"ST's collaboration with Tiempo is now yielding valuable 32-nm silicon feedback; the results validate our assumptions concerning the application of asynchronous design techniques to enable accurate silicon characterization of advanced CMOS processes," said Philippe Magarshack, corporate vice president of design at STMicroelectronics.