Symtavision, specialist tool supplier of timing analysis solutions for planning, optimising and verifying embedded real-time systems, has developed an integrated, model- and trace-based methodology for the Renesas RH850 family of multicore MCUs as well as other Renesas target MCU architectures.
Central to the Symtavision/Renesas integrated methodology for multicore ECUs are Symtavision's SymTA/S tool suite for model-based timing analysis, optimisation and synthesis, combined with Symtavision’s TraceAnalyzer solution for visualising and analysing timing from measurements and simulations. Both SymTA/S and TraceAnalyzer are used in the automotive industry for developing efficient, safe and reliable ECUs, networks and distributed systems.
The methodology involves target tracing to gather fundamental timing data in a realistic environment on the target platform (or one that is predictably related). A range of established tracing tools such as those from Green Hills Software, Gliwa, iSYSTEM or Lauterbach can be used for this purpose. Symtavision’s TraceAnalyzer then processes this data to visualise and validate the internal scheduling of the device and derive key metrics such as memory access times, runnable execution times and patterns of sporadic interrupts. This allows the creation of dedicated RH850 virtual performance models in SymTA/S. These models facilitate an early assessment of design alternatives to ensure that all software can execute in real-time and also provide a basis for the continuous validation of model assumptions versus actual implementation. The dedicated RH850 models ensure that key multicore-related design challenges such as optimal software and task partitioning, as well as data allocation and arbitration, are systematically addressed. The models can be extended seamlessly to analysis of distributed functions over CAN, Ethernet, FlexRay or LIN.
Stephan Reitemeyer, Head of Unit Automotive Control Systems at Renesas Electronics (Europe) GmbH said: “...Establishing a systematic model-based planning and trace-based validation methodology for specific target architectures is crucial to counteract the new timing- and integration-related pitfalls involved in the development of efficient, safe and reliable multicore automotive electronic systems.”